1. Technical Field of the Invention
The present invention relates to an address input buffer, and particularly to an address input buffer device for a random access memory (RAM) device.
2. Background of the Invention
Semiconductor memories, such as random access memories (RAMs) and read-only memories (ROMs), are typically designed synchronous (clocked) or an asynchronous (unclocked) manner. One type of integrated circuit which operates primarily on asynchronous signals is a static random-access memory (SRAM). An SRAM device is designed to receive address values at address terminals, and to statically provide read or write access to memory cells corresponding to the value of the address applied thereto, without relying on a clock signal indicating that the value at its address terminals is valid.
Many modern SRAMs now include edge transition detection (ETD) circuits and other timing and control circuits that provide the SRAM device with performance benefits of internal dynamic operation. An ETD circuit detects transitions within the device and generates internal signals or xe2x80x9cpulsesxe2x80x9d responsive to detecting such transitions. The internally-generated ETD pulses are employed to initialize the SRAM for commencement of a memory read or write cycle.
For example, the use of an ETD circuit allows the SRAM circuit to perform certain internal operations, such as precharging bit lines or deselecting sense amplifiers, after detection of the address transition but before the decoders access the desired cell. Upon presentation of a new memory address to the SRAM, the transitions at the address terminal cause the ETD circuit to enable the necessary functions of the SRAM to access the memory cells selected by the new memory address. An example of an ETD circuit used in SRAMs is described in U.S. Pat. No. 5,124,584, issued on Jun. 23, 1993, assigned to SGS-Thomson Microelectronics and herein incorporated by reference.
Conventional ETD circuitry is not without its shortcomings. For instance, an ETD pulse generated by the ETD circuitry which is utilized to initialize an SRAM device may possess a pulsewidth which is drastically reduced and in some cases eliminated due to input glitches appearing on the address input bus. In addition, ETD circuitry is typically separate and distinct from address input buffer and address decode logic, thereby increasing silicon layout overhead.
Noise or other interference may appear on an input address bus coupled to an SRAM device which may unexpectantly place the input address bus in an undesirable logic state for a temporary period of time. A noise glitch appearing on an input address bus of an SRAM device may propagate through the SRAM address decode circuitry thereof and cause the selection of a false address in which the wrong word line of the SRAM device is asserted. A false address selection may cause data stored in the memory cells associated with the wrong word line to be irretrievably lost.
Accordingly, there is a need for an input address buffer device and method for an SRAM for preventing noise appearing on an address input bus from generating a false address selection and for generating edge transition detection signals with little overhead.
The present invention overcomes shortcomings associated with asynchronous devices and satisfies a need for an input buffer circuit which substantially eliminates the adverse effects of noise and efficiently generates ETD signals for initializing an SRAM or other asynchronous device.
According to the present invention, there is provided an address input buffer device and method for an asynchronous device, such as an SRAM. The address input buffer device preferably receives an input address bus and generates logic true and logic complement output signals representative thereof for use by decoding and other circuitry to which the address input buffer device is coupled, such as row and column decoder circuitry for the SRAM device. In order to prevent the occurrence of false address selection in the corresponding asynchronous SRAM device, the address input buffer circuit preferably includes timing circuitry to first place both of the logic true and complement output signals in a deselected state (i.e., a logic state in which neither the logic true nor logic complement output signals enables an activity within the SRAM device, such as the assertion of a word line). Following a predetermined period of time in which the logic true and complement output signals are in the deselected state, the appropriate one of the logic true and complement output signals transitions to the selected state to enable an activity within the SRAM device.
The above-mentioned timing circuitry of the address input buffer device is efficiently utilized to additionally detect an edge transition appearing on the address input bus and generate an edge transition detection pulse to initialize the SRAM device for preparation of a new memory cycle, such as a memory read or write operation. By generating the edge transition detection pulse from the timing circuitry that generates the logic true and complement signal representations of the input address bus, a relatively sizeable amount of silicon space is saved.